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| To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS07-13506-1E 16-bit Proprietary Microcontroller CMOS F2MC-16F MB90242A Series MB90242A s DESCRIPTION The MB90242A is a 16-bit microcontroller optimized for "mechatronics" control applications such as hard disk drive unit control. The instruction set is based on the AT architecture of the F2MC*-16, 16H family, with additional high-level language supporting instruction, expanded addressing modes, enhanced multiplication and division instructions, and improved bit processing instructions. In addition, long-word data can now be processed due to the inclusion of a 32-bit accumulator. The MB90242A has a multiply/accumulate unit as a peripheral resource, allowing easy realization of digital filters such as IIR or FIR. The MB90242A has abundant embedded peripheral features, such as 6-channel 8/ 10-bit A/D converter, UART, 2-channel + 1-channel timer, 4-channel input capture and 4-channel external interrupt. *1: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES * F2MC-16F CPU Minimum execution time: 62.5 ns (32 MHz oscillation: 5.0 V 10%) Instruction set optimized for controller applications Improved instruction set applicable to high-level language (C) and multitasking Improved execution speed: 8-byte queue Powerful interrupt fuctions (interrupt processing time: 1.0 s 32 MHz oscillation) Automatic transfer function independent of instructions Extended intelligent I/O Service (Continued) s PACKAGE 80-pin Plastic LQFP (FPT-80P-M05) To Top / Lineup / Index MB90242A Series (Continued) * DSP unit Specific function for calculations of IIR A maximum of 8 product resulted from signed 16-bit x 16-bit multiplications can be accumulated. Yk = bn Yk-n + am Xk-m is executed in 0.625 s (at oscillation of 32 MHz, N = M = 3) n=0 m=0 * * * The N and M value is set to a maximum of 3, independently. Internal RAM: 2 Kbytes (MB90242A) Depending on mode settings, data stored on RAM can be executed as CPU instructions. General-purpose ports: max. 38 channels A/D converter (analog inputs: 6 channels) Resolution: 10 bits Conversion time: min. 1.25 s Switchable to 8/10 bits Number of registers for storing conversion results: 4 8-bit UART: 1 channel 8/16-bit I/O simple serial interface (8 Mbps max.): 2 channels 16-bit free-run timer: Operating clock cycle 0.25 s 16-bit input capture: 4 channels Activated by selected edges 16-bit reload timer: 2 channels External interrupts: 4 channels Timebase timer: 18 bits Watchdog timer Clock gear function Low-power consumption modes Sleep mode Stop mode Hardware standby mode Packages: LQFP-80 CMOS 0.8 m technology N M * * * * * * * * * * * * 2 To Top / Lineup / Index MB90242A Series s PRODUCT LINEUP Part number Parameter Classification CPU DSP unit Internal RAM* General-purpose ports A/D converter D/A converter UART 8/16-bit serial I/O 16-bit free-run timer 16-bit input capture 16-bit reload timer External interrupts Timebase timer Watchdog timer Clock gear function Package MB90242A Mass production device F2MC-16F CPU core Built-in 2 Kbytes Max. 38 channels 10-bit resolution, analog inputs: 6 channels None 8 bits: 1 channel 8/16 bits: 1 channel Transfer direction switching function available Built-in 4 channels 2 channels 4 channels Built-in Built-in Built-in FPT-80P-M05 * : The RAM has an extra 64-byte area reserved for multiply/accumulate operations. 3 To Top / Lineup / Index MB90242A Series s PIN ASSIGNMENT (Top view) RST P57/ASR3/INT3 P56/RD P55/WRL P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK P82/INT2/ATG P81/INT1 P80/INT0 P75/SOD1 P74/SID1 P73/SCK1 P72 P71/TOT1 P70/TOT0 HST MD2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS X0 X1 VCC P00/D00 P01/D01 P02/D02 P03/D03 P04/D04 P05/D05 P06/D06 P07/D07 P10/D08 P11/D09 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 MD1 MD0 OPEN OPEN P67/AN7 P66/AN6 P63/AN3 P62/AN2 VSS P61/AN1 P60/AN0 AVSS AVRL AVRH AVCC P47/A23/ASR2 P46/A22/ASR1/TIN1 P45/A21/ASR0/TIN0 P44/A20/SCK0 P43/A19/SOD0 4 P20/A00 P21/A01 P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 VSS P30/A08 P31/A09 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18/SID0 (FPT-80P-M05) To Top / Lineup / Index MB90242A Series s PIN DESCRIPTION Pin no. LQFP* 1 to 8 10 to 17 18 Pin name P20 to P27 A00 to A07 P30 to P37 A08 to A15 P40 F F Circuit type F Function These pins cannot be used as general-purpose ports. Output pins for the lower 8 bits of the external address bus These pins cannot be used as general-purpose ports. Output pins for the middle 8 bits of the external address bus General-purpose I/O port This function is available when corresponding bit of the upper address control register specifies port. External address bus output pin bit 16 This function is available when corresponding bit of the upper address control register specifies address. F General-purpose I/O port This function is available when corresponding bit of the upper address control register specifies port. External address bus output pin bit 17 This function is available when corresponding bit of the upper address control register specifies address. F General-purpose I/O port This function is available when corresponding bit of the upper address control register specifies port. External address bus output pin bit 18 This function is available when corresponding bit of the upper address control register specifies address. UART #0 data input pin This pin, as required, is used for input during UART #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. F General-purpose I/O port This function is available when data output of UART #0 is disabled and corresponding bit of the upper address control register specifies port. External address bus output pin bit 19 This function is available when data output of UART #0 is disabled and corresponding bit of the upper address control register specifies address. UART #0 data output pin This function is available when data output of UART #0 is enabled. A16 19 P41 A17 20 P42 A18 SID0 21 P43 A19 SOD0 * : FPT-80P-M05 (Continued) 5 To Top / Lineup / Index MB90242A Series Pin no. LQFP* 22 Pin name P44 Circuit type F Function General-purpose I/O port This function is available when clock output of UART #0 and SSI #2 are disabled and corresponding bit of the upper address control register specifies port. External address bus output pin bit 20 This function is available when clock output of UART #0 is disabled and corresponding bit of the upper address control register specifies address. UART #0 clock input pin This function is available when the UART #0 clock output is enabled. A20 SCK0 23 P45 F General-purpose I/O port This function is available when data output of SSI #2 is disabled and corresponding bit of the upper address control register specifies port. External address bus output pin bit 21 This function is available when data output of SSI #2 is disabled and corresponding bit of the upper address control register specifies address. Input capature #0 data input pin This pin, as required, is used for input during input capture #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. 16-bit timer #0 data input pin This pin, as required, is used for input during 16-bit timer #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. A21 ASR0 TIN0 24 P46 F General-purpose I/O port This function is available when corresponding bit of the upper address control register specifies port. External address bus output pin bit 22 This function is available when corresponding bit of the upper address control register specifies address. Input capature #1 data input pin This pin, as required, is used for input during input capture #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. 16-bit timer #1 data input pin This pin, as required, is used for input during 16-bit timer #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. A22 ASR1 TIN1 * : FPT-80P-M05 (Continued) 6 To Top / Lineup / Index MB90242A Series Pin no. LQFP* 25 Pin name P47 Circuit type F Function General-purpose I/O port This function is available when corresponding bit of the upper address control register specifies port. External address bus output pin bit 23 This function is available when corresponding bit of the upper address control register specifies address. Input capature #2 data input pin This pin, as required, is used for input during input capture #2 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. A23 ASR2 26 AVCC Power supply Analog circuit power supply pin This power supply must only be turned on or off when electric potential of AVCC or greater is applied to VCC. Power supply A/D converter external reference voltage input pin This pin must only be trendy on or off when electric potential of AVRH or greater is applied to AVCC. Power supply A/D converter external reference voltage input pin Power supply Analog circuit power supply (GND) pin H N-ch open-drain I/O ports When corresponding bit of the ADER are set to "0," reading data register with an instruction other than read-modify-write group instructions reads the level on these pins, while data written on the data register is output on these pins directly. A/D converter analog input pins Set corresponding bit of the ADER to "1," and corresponding bit of the data register to "1." H N-ch open-drain I/O ports When corresponding bit of the ADER are set to "0," reading data register with an instruction other than read-modify-write group instructions reads the level on these pins, while data written on the data register is output on these pins directly. A/D converter analog input pins Set corresponding bit of the ADER to "1," and corresponding bit of the data register to "1." H N-ch open-drain I/O ports When corresponding bit of the ADER are set to "0," reading data register with an instruction other than read-modify-write group instructions reads the level on these pins, while data written on the data register is output on these pins directly. A/D converter analog input pins Set corresponding bit of the ADER to "1," and corresponding bit of the data register to "1." -- Open pins No internal connections are made. 27 AVRH 28 29 30, 31 AVRL AVSS P60, P61 AN0, AN1 33, 34 P62, P63 AN2, AN3 35, 36 P66, P67 AN6, AN7 37, 38 OPEN * : FPT-80P-M05 (Continued) 7 To Top / Lineup / Index MB90242A Series Pin no. LQFP* 39 to 41 42 43, 44 Pin name MD0 to MD2 HST P70, P71 Circuit type C D F Function Operating mode selection input pins Connect directly to VCC or VSS. Hardware standby input pin General-purpose I/O ports This function is available when neither output of 16-bit timer #0 nor #1 is enabled. 16-bit timer output pins This function is available when outputs of both 16-bit timer #0 and #1 are enabled. TOT0, TOT1 45 46 P72 P73 SCK1 F F General-purpose I/O port General-purpose I/O port This function is available when clock output of SSI #1 is disabled. SSI #1 clock I/O pin General-purpose I/O port This function is always valid. SSI #1 data input pin This pin, as required, is used for input during SSI #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. 47 P74 SID1 F 48 P75 SOD1 F General-purpose I/O port This function is available when data output of SSI #1 is disabled. SSI #1 data output pin This function is available when data output of SSI #1 is enabled. 49, 50 P80, P81 INT0, INT1 G General-purpose I/O ports This function is always valid. External interrupt input pins These pins, as required, are used for input while external interrupt is enabled, and it is necessary to disable input/output for other functions from these pins unless such input/output is made intentionally. 51 P82 INT2 F General-purpose I/O port This function is always valid. External interrupt input pin This pin, as required, is used for input while external interrupt is enabled, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. This pin is clamped to "LOW" level when CPU is in the "STOP" status. Use INT0 or INT1 to resume operation. A/D converter activation trigger input pin This pin, as required, is used for input while A/D converter is waiting for activation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. ATG * : FPT-80P-M05 8 (Continued) To Top / Lineup / Index MB90242A Series Pin no. LQFP* 52 Pin name P50 CLK Circuit type F Function General-purpose I/O port This function is available when CLK output is disabled. CLK output pin This function is available when CLK output is enabled. 53 P51 RDY E General-purpose I/O port This function is available when ready function is disabled. Ready input pin This function is available when ready function is enabled. 54 P52 HAK E General-purpose I/O port This function is available when hold function is disabled. Hold acknowledge output pin This function is available when hold function is enabled. 55 P53 HRQ E General-purpose I/O port This function is available when hold function is disabled. Hold request input pin This function is available when hold function is enabled. 56 P54 F General-purpose I/O port This function is available when the external bus 8-bit mode is selected or WRH pin output is disabled. Write strobe output pin for the upper eight bits of the data bus This function is available when the external bus 16-bit mode is selected and WRH pin output is enabled. WRH 57 P55 WRL F General-purpose I/O port This function is available when WRL pin output is disabled. Write strobe output pin for the lower eight bits of the data bus This function is available when WRL pin output is enabled. 58 59 P56 RD P57 ASR3 F F This pin cannot be used as a general-purpose port. Read strobe output pin for the data bus General-purpose I/O port Input capture #3 data input pin This pin, as required, is used for input during input capture #3 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. External interrupt #3 data input pin This pin, as required, is used for input during external interrupt #3 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. INT3 60 62, 63 RST X0, X1 B A External reset request input pin Crystal oscillator pins (32 MHz) * : FPT-80P-M05 (Continued) 9 To Top / Lineup / Index MB90242A Series (Continued) Pin no. LQFP* 64 9, 32, 61 65 to 72 73 to 80 Pin name VCC VSS P00 to P07 D00 to D07 P10 to P17 E Circuit type Function Power supply Digital circuit power supply pin Power supply Digital circuit power supply (GND) pins E These pins cannot be used as general-purpose ports. I/O pins for the lower 8 bits of the external data bus General-purpose I/O ports This function is available when the external bus 8-bit mode is selected. I/O pins for the upper 8 bits of the external data bus This function is available when the 16-bit bus mode is selected. D08 to D15 * : FPT-80P-M05 10 To Top / Lineup / Index MB90242A Series s I/O CIRCUIT TYPE Type A Circuit Remarks * 32 MHz * Oscillation feedback resistor: approx. 1 M Clock stop input X0 X1 Clock input B VCC P-channel-type Tr N-channel-type Tr Diffused resistor VSS Digital input CMOS * CMOS-level hysteresis input (without standby control) Pull-up resistor: approx. 50 k C VCC P-channel-type Tr N-channel-type Tr Diffused resistor VSS Digital input CMOS * CMOS-level input (without standby control) D VCC P-channel-type Tr N-channel-type Tr Diffused resistor VSS Digital input CMOS * CMOS-level hysteresis input (without standby control) (Continued) 11 To Top / Lineup / Index MB90242A Series Type E Circuit Remarks * CMOS-level output * TTL-Level input (with standby control) Digital output Digital output Digital input TTL Standby control signal F Digital output Digital output * CMOS-level input CMOS-level hysteresis input (with standby control) Digital input CMOS Standby control signal G Digital output Digital output * CMOS-level output CMOS-level hysteresis input Standby control (when interrupt disabled) available Digital input CMOS interrupt disabled Standby H Digital output * N-ch open-drain CMOS-level output CMOS-level hysteresis input Analog input (with analog input control) Analog output Digital input ADER CMOS (Continued) 12 To Top / Lineup / Index MB90242A Series (Continued) Type I Digital output Circuit Remarks * CMOS-level input Analog input * CMOS-level hysteresis input (with standby control) Digital output Analog input Digital output CMOS Standby control signal 13 To Top / Lineup / Index MB90242A Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input or output pins other than medium-and high voltage pins or if higher than the voltage is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. In addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power supply. 2. Treatment of Unused Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistors. 3. Precautions when Using an External Clock When an external clock is used, drive X0 only and X1 should be left open. * Using an External Clock X0 MB90242A X1 4. Power Supply Pins When there are several VCC and VSS pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latchup. However, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with the lowest possible impedance. Finally, it is recommended to connect a capacitor of about 0.1 F between VCC and VSS near this device as a bypass capacitor. 14 To Top / Lineup / Index MB90242A Series 5. Crystal Oscillation Circuit Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible. In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended. 6. CLK Pin ex. 32 MHz X1 STOP to internal blocks X0 Divide by 2 circuit P50/CLK* P50 output P50 input CLK output * : In the external bus mode, the P50/CLK pin is initially configured as a CLK output pin. 7. Cautions in Applying Power Supply Hold the HST pin to the "H" level when applying power supply. When the RST pin is in the "L" level, do not hold the HST pin to "L" level. 15 To Top / Lineup / Index MB90242A Series s BLOCK DIAGRAM SCK0 SID0 SOD0 3 UART 16-bit timer SCK1 SID1 SOD1 Simple serial 4 ASR0 to ASR3 ICU x 4 F2MC-16F bus AVCC AVRH AVRL AVSS AN0 to AN3 AN6 AN7 ATG 11 A/D converter I/O port x 38 63 Multiply/accumulate module External bus interface 16 24 4 2 TIN0, TIN1 2 TOT0, TOT1 16-bit timer x 3 P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63, P66, P67, P70 to P75 P80 to P82 D00 to D15 A00 to A23 CLK RDY HAK HRQ WRH WRL RD F2MC-16F CPU RAM 4 INT0 to INT3 External interrupt timer x 4 X0 X1 RST HST MD2 to MD0 7 Clock controller 16 To Top / Lineup / Index MB90242A Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Power supply voltage Input voltage Output voltage "L" level output current "L" level average output current "L" level total average output current "H" level output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature * : VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC AVCC VI* VO* IOL IOLAV IOLAV IOH IOHAV IOHAV PD TA Tstg Value Min. VSS - 0.3 VCC - 0.3 VSS - 0.3 VSS - 0.3 -30 -55 Max. VSS + 7.0 VCC + 7.0 VCC + 0.3 VCC + 0.3 10 4 50 -10 -4 -48 600 +70 +150 Unit V V V V mA mA mA mA mA mA mW C C Remarks 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol Value Min. 4.5 Power supply voltage Operating temperature VCC TA 2.0 -30 Max. 5.5 5.5 +70 Unit V V C For retaining RAM data in the stop mode External bus mode Remarks WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 17 To Top / Lineup / Index MB90242A Series 3. DC Characteristics (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Typ. Max. -- -- -- -- -- -- -- -- 0.7 VCC 2.2 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5 -- -- -- -- -- -- -- 22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 30 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.8 0.2 VCC VSS + 0.3 -- 0.4 -10 -10 -10 10 10 10 110 100 50 V V V V V V V V V V A A A A A A k mA mA In operation mode CMOS input TTL input Hysteresis input CMOS input TTL input Hysteresis input CMOS input TTL input Hysteresis input CMOS input TTL input Hysteresis input Parameter Symbol VIH1 Pin name -- -- -- MD0 to MD2 -- -- -- MD0 to MD2 "H" level input voltage VIH2 VIHIS VIHM VIL1 VIL2 VILIS VILM "L" level input voltage "H" level output voltage "L" level output voltage VOH VOL IIH1 All ports except VCC = 4.5 V P60 to P63, IOH = -4.0 mA P66, P67 All ports Except RST -- -- Except RST -- -- VCC = 4.5 V IOL = 4.0 mA VCC = 5.5 V VIH = 0.7 VCC VCC = 5.5 V VIH = 2.2 V VCC = 5.5 V VIH = 0.8 VCC VCC = 5.5 V VIL = 0.3 VCC VCC = 5.5 V VIL = 0.8 VCC VCC = 5.5 V VIL = 0.2 VCC VCC = 5.0 V VCC = 5.0 V 10% FC = 32 MHz VCC = 5.0 V 10% FC = 32 MHz In sleep mode VCC = 5.0 V 10% TA = +25C In stop mode -- -- "H" level input current IIH2 IIH3 IIL1 "L" level input current IIL2 IIL3 Pull-up resistor RPULL RST ICC VCC VCC Power supply current ICCS ICCH Input capacitance Open-drain output leakage current CIN ILEAK VCC Except VCC, VSS P60 to P63, P66, P67 -- -- -- 0.1 10 0.1 10 -- 10 A pF A 18 To Top / Lineup / Index MB90242A Series 4. AC Characteristics (1) Clock Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- 1/FC 10 -- 32 -- -- 8 MHz ns ns ns Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/ falling time Symbol FC tC PWH PWL tCR tCF Pin name X0 X1 X0 X1 X0 X0 * Clock Timing tC 0.7 VCC 0.3 VCC PWH tCF PWL tCR * Relationship between Clock Frequency and Supply Voltage VCC [V] Operating garantee range (TA = -30C to +70C, external bus mode) 5.5 4.5 0 32 FC [MHz] 19 To Top / Lineup / Index MB90242A Series (2) Clock Output Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- tC x 2 tCYC/2 - 20 -- tCYC/2 ns ns Parameter Machine cycle time CLK CLK Symbol tCYC tCHCL Pin name CLK CLK tCYC tCHCL CLK (3) Reset and Hardware Standby Input (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- tCYC x 5 tCYC x 5 -- -- ns ns Parameter Reset input time Hardware standby input time Symbol tRSTL tHSTL Pin name RST HST Note: The machine cycle time (tCYC) at hardware standby is set to 1/32 divided oscillation. tRSTL, tHSTL RST HST 20 To Top / Lineup / Index MB90242A Series (4) Power-on Reset (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- 1 30 -- ms ms VCC must be lower than 0.2 V before power is applied. Parameter Symbol Pin name Power supply rising time Power supply cut-off time tR tOFF VCC VCC Note: The above standards are the values needed in order to activate a power-on reset. tR VCC +2.97 V +0.2 V tOFF If power supply voltage needs to be changed in the course of operation, a smooth voltage rise is recommended by suppressing the voltage variation as shown below. 5.0 V It is recommended that the rate of increase in the voltage be kept to no more that 50 mV/ms. VCC 2.0 V Holding RAM data VSS 21 To Top / Lineup / Index MB90242A Series (5) Bus Read Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- D00 to D15 Address Address CLK RD, CLK -- -- -- -- -- 2 tCYC - 10 tCYC/2 - 15 tCYC - 25 -- 0 -- tCYC/2 - 20 tCYC/2 - 25 tCYC/2 - 25 -- -- -- tCYC/ - 30 -- 3 tCYC/2 - 40 -- -- -- ns ns ns ns ns ns ns ns ns Parameter Address cycle time Valid address RD time RD pulse width RD Valid data input RD data hold time Valid address Valid data input RD Address valid time Valid address CLK time RD CLK time Symbol Pin name tACYC tAVRL tRLRH tRLDV tRHDX tAVDV tRHAX tAVCH tRLCL Address Address RD tAVCH tRLCL CLK tAVRL tRLRH tACYC RD tRHAX Address tRLDV tAVDV Data 2.2 VCC 0.8 VCC tRHDX 22 To Top / Lineup / Index MB90242A Series (6) Bus Write Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- -- tCYC/2 - 15 tCYC - 25 tCYC - 40 tCYC/2 - 15 tCYC/2 - 15 tCYC/2 - 25 -- -- -- -- -- -- ns ns ns ns ns ns Parameter Valid address WR time WR pulse width Write data WR time WR Data hold time Symbol Pin name tAVWL tWLWH tDVWH tWHDX Address WRL, WRH D00 to D15 D00 to D15 Address WRL, WRH, CLK WR Address invalid time tWHAX WR CLK time tWLCL tWLCL CLK tAVWL WR (WRL, WRH) tWLWH tWHAX Address tDVWH tWHDX 0.8 VCC Data Write data 2.2 VCC 23 To Top / Lineup / Index MB90242A Series (7) Ready Input Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. At 32 MHz oscillation 15 0 60 60 ns ns Parameter RDY setup time RDY hold time Symbol Pin name tRYHS tRYHH RDY RDY Note: If the setup time of RDY on a falling edge is insufficient, use the auto ready function. CLK RD/WR tRYHH RDY tRYHS A23 to A00 External address D15 to D00 Wait cycle Read data D15 to D00 Wait cycle Write data 24 To Top / Lineup / Index MB90242A Series (8) Hold Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- 30 tCYC tCYC 2 tCYC ns ns Parameter Pin floating HAK time HAK time Pin valid time Symbol Pin name tXHAL tHAHV HAK HAK Note: At least one cycle is required from the time when HRQ is fetched until HAK changes. HRQ HAK tXHAL Each pin High impedance tHAHV 25 To Top / Lineup / Index MB90242A Series (9) UART Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- -- -- -- -- -- 8 tCYC -80 100 60 4 tCYC 4 tCYC -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns For external shift clock mode output pin, CL = 80 pF For internal shift clock mode output pin, CL = 80 pF Parameter Symbol Pin name -- -- -- -- -- -- -- -- -- Serial clock cycle time tSCYC SCK SOD delay time Valid SID SCK SCK Valid SID hold time tSLOV tIVSH tSHIX Serial clock "H" pulse tSHSL width Serial clock "L" pulse width SCK SOD delay time Valid SID SCK SCK Valid SID hold time tSLSH tSLOV tIVSH tSHIX Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance added to pins during testing. * tCYC is the machine cycle time (unit: ns). 26 To Top / Lineup / Index MB90242A Series * Internal Shift Clock Mode tSCYC SCK0 tSLOV SOD0 tIVSH tSHIX SID0 * External Shift Clock Mode tSLSH SCK0 tSHSL tSLOV SOD0 tIVSH tSHIX SID0 27 To Top / Lineup / Index MB90242A Series (10) Simple Serial Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- -- -- -- 2 tCYC -- 1 tCYC 1 tCYC -- tCYC/2 -- -- ns ns ns ns For operation output pin, CL = 80 pF Parameter Serial clock cycle time SCK SOD delay time Valid SID SCK Symbol tSCYC tSLOV tIVSH Pin name -- -- -- -- SCK Valid SID hold time tSHIX Notes: * CL is the load capacitance added to pins during testing. * tCYC is the machine cycle time (unit: ns). * Internal Shift Clock Mode tSCYC SCK1 tSLOV SOD1 tIVSH tSHIX SID1 (11) Timer Input Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Condition Unit Remarks Min. Max. -- 4 tCYC -- ns Parameter Input pulse width Symbol tTIWH tTIWL Pin name ASR0 to ASR3, TIN0 to TIN2 ASR0 to ASR3 TIN0 to TIN2 tTIWH tTIWL 28 To Top / Lineup / Index MB90242A Series (12) Timer Ouput Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Parameter SCK Change time Symbol tTO Pin name TOT0, TOT1 Condition VCC = 5.0 V 10% Value Min. -- Max. 40 Unit ns Remarks CLK TOT0, TOT1 tTO (13) Trigger Input Timing (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Parameter Input pulse width Symbol tTRGH tTRGL Pin name ATG, INT0 to INT3 Condition -- Value Min. 5 tCYC Max. -- Unit ns Remarks ATG INT0 to INT3 tTRGH tTRGL 29 To Top / Lineup / Index MB90242A Series 5. A/D Converter Electrical Characteristics (VCC = 5.0 V 10%, VSS = 0.0 V, TA = -30C to +70C) Value Unit Remarks Min. Typ. Max. -- -- -- -- 8, 10 -- -- -- AVRL + 1.0 AVRH - 1.0 -- -- -- -- -- 0.1 -- -- -- 15 -- 1.5 -- -- 10 3.0 2.0 1.9 AVRL + 3.0 AVRH + 1.0 -- -- -- -- -- 3 AVRH AVCC AVRH - 2.7 20 5 2 5 4 bit LSB LSB LSB LSB LSB s ns ns ns ns A V V V mA A mA A LSB AVCC = 5.5 V in stop mode AVCC = 5.5 V in stop mode AVRH - AVRL 2.7 Specified by the ADCT register settings.*1 VCC = 5.0 V10% Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling period Conversion period a Conversion period b Conversion period c Analog port input current Analog input voltage Reference voltage Symbol -- -- -- -- VOt VFST -- -- -- -- -- IAIN -- -- -- IA Pin name -- -- -- -- AN0 to AN3 AVRL - 1.0 AN6, AN7 AN0 to AN3 AVRH - 4.0 AN6, AN7 -- -- -- -- -- AN0 to AN3 AN6, AN7 AN0 to AN3 AN6, AN7 AVRH AVRL AVCC 1.25 560 125 125 250 -- AVRL AVRL + 2.7 0 -- -- -- AVRH AN0 to AN3 AN6, AN7 -- -- Power supply current IAS*2 IR IRS*2 -- Reference voltage supply current Interchannel disparity *1: When FC = 32 MHz, and the machine cycle is 62.5 ns. *2: IAS and IRS are current when the A/D converter is not operating and the CPU is stopped. Notes: * The smaller | AVRH - AVRL |, the greater the error would become relatively. * If the output impedance of the external circuit of an analog input is too high, an analog voltage sampling time might be insufficient. When the sampling period close to the minimum value is used, the output impedance of the external circuit should be less than approximately 300 . 30 To Top / Lineup / Index MB90242A Series * Analog Input Circuit Model Diagram C0 Approx. 60 pF Analog input pin RON2 RON1 Approx. 300 Approx. 150 Switched on only during A/D conversion. AVRH Approx. 4 pF C1 Comparator Comparator . . Comparator AVRL Note: Use the values shown as guides only. 31 To Top / Lineup / Index MB90242A Series 6. A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter. If the resolution is 10 bits, the analog voltage can be resolved into 210. * Total error The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, non-linearity error, differential linearity error, and noise. * Linearity error The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics. * Differential linearity error The deviation of input voltage needed to change the output by 1 LSB from the theoretical value. Digital output 11 1111 1111 11 1111 1110 * * * * * * * * * * * * (1 LSB x N + VOT) Linearity error 11 1111 1110 00 0000 0001 00 0000 0000 VOT VNT V(N+1)T VFST * 1 LSB = VFST - VOT 1022 VNT - (1 LSB x N + VOT) 1 LSB (LSB) * Linearity error = * Differential linearity error = V(N+1)T - VNT -1 (LSB) 1 LSB 32 To Top / Lineup / Index MB90242A Series s INSTRUCTION SET (412 INSTRUCTIONS) Table 1 Item Mnemonic Explanation of Items in Table of Instructions Explanation Upper-case letters and symbols: Represented as they appear in assembler Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. See Table 4 for details about meanings of letters in items. Indicates the correction value for calculating the number of actual cycles during execution of instruction. The number of actual cycles during execution of instruction is summed with the value in the "cycles" column. Indicates operation of instruction. Indicates special operations involving the bits 15 through 08 of the accumulator. Z: Transfers "0". X: Extends before transferring. --: Transfers nothing. Indicates special operations involving the high-order 16 bits in the accumulator. *: Transfers from AL to AH. --: No transfer. Z: Transfers 00H to AH. X: Transfers 00H or FFH to AH by extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). *: Changes due to execution of instruction. --: No change. S: Set by execution of instruction. R: Reset by execution of instruction. # ~ B Operation LH AH I S T N Z V C RMW Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: Instruction is a read-modify-write instruction --: Instruction is not a read-modify-write instruction Note: Cannot be used for addresses that have different meanings depending on whether they are read or written. 33 To Top / Lineup / Index MB90242A Series Table 2 Symbol A Explanation of Symbols in Table of Instructions Explanation 32-bit accumulator The number of bits used varies according to the instruction. Byte: Low order 8 bits of AL Word: 16 bits of AL Long: 32 bits of AL, AH High-order 16 bits of A Low-order 16 bits of A Stack pointer (USP or SSP) Program counter Stack pointer upper limit register Stack pointer lower limit register Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) AH AL SP PC SPCU SPCL PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 io (Continued) 34 To Top / Lineup / Index MB90242A Series (Continued) Symbol #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst Explanation 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value Vector number (0 to 15) Vector number (0 to 255) Bit address Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list 35 To Top / Lineup / Index MB90242A Series Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extemsion* -- @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 addr16 Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacemen 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 * : The number of bytes for address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the Table of Instructions. 36 To Top / Lineup / Index MB90242A Series Table 4 Code 00 to 07 Number of Execution Cycles for Each Form of Addressing Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + dip16 @addr16 (a)* Number of execution cycles for each from of addressing Listed in Table of Instructions 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F 1 4 1 1 2 2 2 1 * : "(a)" is used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal RAM even address Internal RAM odd address Even address not in internal RAM Odd address not in internal RAM External data bus (8 bits) + + + + + + (b)* byte 0 0 0 1 1 1 + + + + + + (c)* word 0 0 1 1 3 3 + + + + + + (d)* long 0 0 2 2 6 6 * : "(b)", "(c)", and "(d)" are used in the "cycles" (number of cycles) column and column B (correction value) in the Table of Instructions. 37 To Top / Lineup / Index MB90242A Series Table 6 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOVP MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, @SP+disp8 A, addr24 A, @A A, #imm4 # cycles Transfer Instructions (Byte) [50 Instructions] B (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi))+disp8) byte (A) ((RLi))+disp8) byte (A) ((SP)+disp8) byte (A) (addr24) byte (A) ((A)) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi)) +disp8) (A) byte ((SP)+disp8) (A) byte (addr24) (A) byte (Ri) (ear) byte (Ri) (eam) byte ((A)) (Ri) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) LH AH I Z Z Z Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X X X X - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - * * * * * * * * - * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 2 3 2 1 1 2 1 2+ 2+ (a) 2 2 2 2 2 2 3 6 3 3 5 3 2 2 1 1 MOVX A, dir 2 2 MOVX A, addr16 3 2 MOVX A, Ri 2 1 MOVX A, ear 2 1 MOVX A, eam 2+ 2+ (a) MOVX A, io 2 2 MOVX A, #imm8 2 2 MOVX A, @A 2 2 MOVX A,@RWi+disp8 2 3 MOVX A, @RLi+disp8 3 6 MOVX A, @SP+disp8 3 3 MOVPX A, addr24 5 3 MOVPX A, @A 2 2 MOV MOV MOV MOV MOV MOV MOV MOV MOVP MOV MOV MOVP MOV MOV MOV MOV MOV MOV MOV MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A @SP+disp8, A addr24, A Ri, ear Ri, eam @A, Ri ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH 2 2 3 2 1 1 2 2 2+ 2+ (a) 2 2 3 6 3 3 5 3 2 2 2+ 3+ (a) 2 3 2 3 2+ 3+ (a) 2 2 3 3 3 3 3 2 3+ 2+ (a) 2 2 (Continued) 38 To Top / Lineup / Index MB90242A Series (Continued) Mnemonic XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam # cycles B Operation byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) LH AH I Z Z - - - - - - - - - - S - - - - T - - - - N - - - - Z - - - - V - - - - C RMW - - - - - - - - 2 3 0 2+ 3+ (a) 2x (b) 2 4 0 2+ 5+ (a) 2x (b) For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 39 To Top / Lineup / Index MB90242A Series Table 7 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVPW MOVPW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVPW MOVPW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, @SP+disp8 A, addr24 A, @A dir, A addr16, A SP, # imm16 SP, A RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A @SP+disp8, A addr24, A @A, RWi RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 # Transfer Instructions (Word) [40 Instructions] B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (A) ((SP) +disp8 word (A) (addr24) word (A) ((A)) word (dir) (A) word (addr16) (A) word (SP) imm16 word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word ((SP) +disp8) (A) word (addr24) (A) word ((A)) (RWi) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - cycles 2 2 3 2 1 2 1 1 2 1 2+ 2+ (a) 2 2 2 2 3 2 2 3 3 6 3 3 5 3 2 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2 MOVW @AL, AH XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 2 3 0 2+ 3+ (a) 2x (c) 2 4 0 2+ 5+ (a) 2x (c) Note: For an explanation of "(a)" and "(c)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 40 To Top / Lineup / Index MB90242A Series Table 8 Mnemonic MOVL MOVL MOVL MOVL MOVPL MOVPL # Transfer Instructions (Long Word) [11 Instructions] B 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) Operation long (A) (ear) long (A) (eam) long (A) imm32 long (A) ((SP) +disp8) long (A) (addr24) long (A) ((A)) long ((A)) (RLi) long ((SP) + disp8) (A) long (addr24) (A) long (ear) (A) long (eam) (A) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - cycles A, ear 2 1 2+ 3+ (a) A, eam 5 3 A, # imm32 4 A, @SP + disp8 3 5 4 A, addr24 A, @A 2 3 2 5 MOVPL @A, RLi MOVL MOVPL MOVL MOVL @SP + disp8, A 3 4 addr24, A 5 4 ear, A 2 2 eam, A 2+ 3+ (a) For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 41 To Top / Lineup / Index MB90242A Series Table 9 Mnemonic ADD A, #imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # cycles B Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (Decimal) byte (A) (A) -imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (Decimal) word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 LH AH I Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C RMW * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - * * - - - - - - - - 2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0 2 2 0 2 3 (b) 2 2 0 2+ 3+ (a) (b) 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) (b) 1 3 0 ADDW A 1 2 0 ADDW A, ear 2 2 0 ADDW A, eam 2+ 3+ (a) (c) ADDW A, #imm16 3 2 0 ADDW ear, A 2 2 0 ADDW eam, A 2+ 3+ (a) 2x (c) ADDCW A, ear 2 2 0 ADDCW A, eam 2+ 3+ (a) (c) SUBW A 1 2 0 SUBW A, ear 2 2 0 SUBW A, eam 2+ 3+ (a) (c) SUBW A, #imm16 3 2 0 SUBW ear, A 2 2 0 SUBW eam, A 2+ 3+ (a) 2x (c) SUBCW A, ear 2 2 0 SUBCW A, eam 2+ 3+ (a) (c) ADDL ADDL ADDL SUBL SUBL SUBL A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 A, ear 2 5 A, eam 2+ 6+ (a) A, #imm32 5 4 0 (d) 0 0 (d) 0 For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 42 To Top / Lineup / Index MB90242A Series Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # cycles B Operation LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C RMW - - - - - - - - - - - - * * * * * * * * * * * * 2 2 0 byte (ear) (ear) +1 2+ 3+ (a) 2x (b) byte (eam) (eam) +1 2 2 0 byte (ear) (ear) -1 2+ 3+ (a) 2x (b) byte (eam) (eam) -1 2 2 0 word (ear) (ear) +1 2+ 3+ (a) 2x (c) word (eam) (eam) +1 2 2 0 word (ear) (ear) -1 2+ 3+ (a) 2x (c) word (eam) (eam) -1 2 4 0 long (ear) (ear) +1 2+ 5+ (a) 2x (d) long (eam) (eam) +1 2 4 0 long (ear) (ear) -1 2+ 5+ (a) 2x (d) long (eam) (eam) -1 DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] cycles B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 long (A) - (ear) long (A) - (eam) long (A) - imm32 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C RMW * * * * * * * * * * * - - - - - - - - - - - 1 2 2 2 2+ 2+ (a) 2 2 1 2 2 2 2+ 2+ (a) 3 2 2 3 2+ 4+ (a) 5 3 CMPL A, ear CMPL A, eam CMPL A, #imm32 For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 43 To Top / Lineup / Index MB90242A Series Table 12 Mnemonic DIVU DIVU DIVU A A, ear Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions] # 1 2 cycles * 1 B Operation LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N - - - - - - - - - - - Z - - - - - - - - - - - V C RMW * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - *2 *3 *4 *5 A, eam 2+ 2 DIVUW A, ear DIVUW A, eam 2+ MULU MULU MULU MULUW MULUW MULUW A A, ear A, eam A A, ear A, eam 1 2 2+ 1 2 2+ 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A) *8 *9 *10 *11 *12 *13 For an explanation of "(b)" and "(c), refer to Table 5, "Correction Values for Number of Cycle Used to Calculate Number of Actual Cycles." *1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. *2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. *3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. *4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. *5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. *8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0. *9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. *10:4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. *11:3 when word (AH) is zero, and 11 when word (AH) is not 0. *12:3 when word (ear) is zero, and 11 when word (ear) is not 0. *13:4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. 44 To Top / Lineup / Index MB90242A Series Table 13 Mnemonic DIV DIV DIV DIVW DIVW A A, ear Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions] # cycles B 2 2 * 1 Operation LH AH I Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N - - - - - - - - - - - Z - - - - - - - - - - - V * * * * * - - - - - - C RMW * * * * * - - - - - - - - - - - - - - - - - *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 A, eam 2+ A, ear 2 A, eam 2+ 0 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (b) byte (AH) x byte (AL) word (A) byte (A) x byte (ear) word (A) byte (A) x byte (eam) word (A) word (AH) x word (AL) long (A) word (A) x word (ear) long (A) word (A) x word (eam) long (A) MUL A 2 MUL A, ear 2 MUL A, eam 2+ MULW A 2 MULW A, ear 2 MULW A, eam 2+ For an explanation of "(b)" and "(c)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 x (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 x (c) normally. *8: 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10:4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11:3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12:3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13:4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation. 45 To Top / Lineup / Index MB90242A Series Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # cycles Logical 1 Instructions (Byte, Word) [39 Instructions] B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - - - * * - - - * * - * * - - - - * * - - - - * * - - - - * * - * * 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 2 2 0 2 2 0 2+ 3+ (a) (b) 2 3 0 2+ 3+ (a) 2x (b) 1 2 0 2 2 0 2+ 3+ (a) 2x (b) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 3 2 0 2 2 0 2+ 3+ (a) (c) 2 3 0 2+ 3+ (a) 2x (c) 1 2 0 2 2 0 2+ 3+ (a) 2x (c) For an explanation of "(a)", "(b)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 46 To Top / Lineup / Index MB90242A Series Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # cycles Logical 2 Instructions (Long Word) [6 Instructions] B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH I - - - - - - - - - - - - - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RMW - - - - - - - - - - - - 2 5 2+ 6+ (a) 2 5 2+ 6+ (a) 2 5 2+ 6+ (a) XORL A, ear XORL A, eam For an explanation of "(a)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 16 Mnemonic NEG NEG NEG A ear eam # 1 Sign Inversion Instructions (Byte/Word) [6 Instructions] B 0 Operation byte (A) 0 - (A) LH AH I X - - - - - - - - - - - - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C RMW * * * * * * - * * - * * cycles 2 2 2 0 byte (ear) 0 - (ear) 2+ 3+ (a) 2x (b) byte (eam) 0 - (eam) 1 2 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam 2 2 0 word (ear) 0 - (ear) 2+ 3+ (a) 2x (c) word (eam) 0 - (eam) For an explanation of "(a)", "(b)" and "(c)" and refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 17 Mnemonic ABS A ABSW A ABSL A # 2 2 2 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions] cycles 2 2 4 B 0 0 0 Operation byte (A) absolute value (A) word (A) absolute value (A) long (A) absolute value (A) LH AH I Z - - - - - - - - S - - - T - - - N * * * Z * * * V * * * C RMW - - - - - - Table 18 Mnemonic NRML A, R0 # 2 cycles * B 0 Normalize Instructions (Long Word) [1 Instruction] Operation long (A) Shifts to the position at which "1" was set first byte (R0) current shift count LH AH I - - - S - T * N - Z - V - C RMW - - * : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases. 47 To Top / Lineup / Index MB90242A Series Table 19 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0 A, #imm8 A, #imm8 A, #imm8 # cycles 2 2 2 2 Shift Instructions (Byte/Word/Long Word) [27 Instructions] B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - * * - * * - N * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * V - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * * * * - - - - - - - - - - - - - - - - - - - - - 0 2 2 2+ 3+ (a) 2x (b) 0 2 2 2+ 3+ (a) 2x (b) 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3 2 2 2 3 3 3 *1 *1 *1 *3 *3 *3 2 2 2 *1 *1 *1 *3 *3 *3 *2 *2 *2 *4 *4 *4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (A) Arithmetic right barrel shift (A, R0) - byte (A) Logical right barrel shift (A, R0) - byte (A) Logical left barrel shift (A, R0) - - byte (A) Arithmetic right barrel shift (A, imm8) byte (A) Logical right barrel shift (A, imm8) - byte (A) Logical left barrel shift (A, imm8) - word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) - - - ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRW A, #imm8 LSRW A, #imm8 LSLW A, #imm8 ASRL A, R0 LSRL A, R0 LSLL A, R0 ASRL LSRL LSLL A, #imm8 A, #imm8 A, #imm8 ** *R -* * * - * * - * * - * * - * * * * * * * * * * * * word (A) Arithmetic right barrel shift (A, R0) - word (A) Logical right barrel shift (A, R0) - word (A) Logical left barrel shift (A, R0) - word (A) Arithmetic right barrel shift (A, imm8) - word (A) Logical right barrel shift (A, imm8) - word (A) Logical left barrel shift (A, imm8) - long (A) Arithmetic right shift (A, R0) - long (A) Logical right barrel shift (A, R0) - long (A) Logical left barrel shift (A, R0) - long (A) Arithmetic right shift (A, imm8) - long (A) Logical right barrel shift (A, imm8) - long (A) Logical left barrel shift (A, imm8) - For an explanation of "(a)" and "(b)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: 3 when R0 is 0, 3 + (R0) in all other cases. *2: 3 when R0 is 0, 4 + (R0) in all other cases. *3: 3 when imm8 is 0, 3 + (imm8) in all other cases. *4: 3 when imm8 is 0, 4 + (imm8) in all other cases. 48 To Top / Lineup / Index MB90242A Series Table 20 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 cycles *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 2 3 4+ (a) 3 4+ (a) 3 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Branch 1 Instructions [31 Instructions] Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 ( (V) xor (N) ) or (Z) = 1 ( (V) xor (N) ) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15 (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call linstruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr 0 to 15, (PCB) addr 16 to 23 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 2 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 2+ 4 4 (c) 5+ (a) 2x (c) 5 (c) 5 2x (c) 7 2x (c) 8+ (a) 7 *2 2x (c) CALLP @eam *6 CALLP addr24 *7 For an explanation of "(a)", "(c)" and "(d)", refer to Table 4, "Number of Execution Cycles for Each Form of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: 3 when branching, 2 when not branching. *2: 3 x (c) + (b) *3: Read (word) branch address. *4: W: Save (word) to stack; R: Read (word) branch address. *5: Save (word) to stack. *6: W: Save (long word) to W stack; R: Read (long word) branch address. *7: Save (long word) to stack. 49 To Top / Lineup / Index MB90242A Series Table 21 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ # 3 4 cycle *1 *1 *1 *3 *1 *3 *2 *4 *2 *4 14 12 13 14 9 11 6 B 0 0 0 (b) 0 (c) 0 Branch 2 Instructions [20 Instructions] Operation Branch when byte (A) imm8 Branch when byte (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - R R R R * * - S - - - - - - - - - - S S S S * * - T - - - - - - - - - - - - - - * * - N * * * * * * * * * * - - - - * * - Z * * * * * * * * * * - - - - * * - V * * * * * * * * * * - - - - * * - C RMW * * * * * * - - - - - - - - * * - - - - - - - - * - * - - - - - - - 4 ear, #imm8, rel eam, #imm8, rel 4+ 5 ear, #imm16, rel eam, #imm16, rel 5+ ear, rel eam, rel 3 3+ 3 3+ 2 3 4 1 1 2 2 DWBNZ ear, rel DWBNZ eam, rel INT #vct8 INT addr16 INTP addr24 INT9 RETI RETIQ *6 LINK #imm8 Branch when byte (ear) = (ear) - 1, and (ear) 0 2x (b) Branch when byte (ear) = (eam) - 1, and (eam) 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) *5 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt UNLINK 1 1 1 5 4 5 (c) (c) (d) At constant entry, save old frame - pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame - pointer from stack. Return from subroutine Return from subroutine - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RET *7 RETP *8 For an explanation of "(b)", "(c)" and "(d)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: 4 when branching, 3 when not branching *2: 5 when branching, 4 when not branching *3: 5 + (a) when branching, 4 + (a) when not branching *4: 6 + (a) when branching, 5 + (a) when not branching *5: 3 x (b) + 2 x (c) when an interrupt request is generated, 6 x (c) when returning from the interrupt. *6: High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: Return from stack (word) *8: Return from stack (long word) 50 To Top / Lineup / Index MB90242A Series Table 22 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A Other Control Instructions (Byte/Word/Long Word) [36 Instructions] B (c) (c) (c) *4 (c) (c) (c) *4 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)) , (SP) (SP) LH AH I - - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - N - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - - - - Z - - - - - - * - * * * - - - - - - - - * * * - - - - - - - - - - - * * * V - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # cycles 1 1 1 2 1 1 1 2 1 3 3 3 *3 3 3 3 *2 9 3 3 2 2 6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR, #imm8 2 CCR, #imm8 2 2 2 byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) ext (imm8) word (SP) imm16 byte (A) (brgl) byte (brg2) (A) byte (brg2) imm8 No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for no flag change Prefix code for the common register bank word (SPCU) (imm16) word (SPCL) (imm16) Stack check ooperation enable Stack check ooperation disable - - - - - - - - Z - - - - - - - - - - - - - MOV RP, #imm8 MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV MOV NOP ADB DTB PCB SPB NCC CMR MOVW SPCU, #imm16 MOVW SPCL, #imm16 SETSPC CLRSPC BTSCN A BTSCNS A BTSCND A A, brgl brg2, A brg2, #imm8 2 3 2+ 2+ (a) 2 2 2+ 1+ (a) 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7 byte (A) position of "1" bit in word (A) Z byte (A) position of "1" bit in word (A) x 2 Z byte (A) position of "1" bit in word (A) x 4 Z For an explanation of "(a)" and "(c)", refer to Tables 4 and 5. *1: PCB, ADB, SSB, USB, and SPB: 1 cycle *4: DTB: 2 cycles *5: DPR: 3 cycles *6: *2: 3 + 4 x (pop count) *7: *3: 3 + 4 x (push count) Pop count x (c), or push count x (c) 3 when AL is 0, 5 when AL is not 0. 4 when AL is 0, 6 when AL is not 0. 5 when AL is 0, 7 when AL is not 0. 51 To Top / Lineup / Index MB90242A Series Table 23 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 cycles 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I Z Z Z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - N * * * * * * - - - - - - - - - - - - - - - Z * * * * * * - - - - - - * * * * * * * - - V - - - - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - 2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 2x (b) Branch when (addr16:bp) b = 1, bit = 1 *4 *4 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 WBTS io:bp WBTC io:bp For an explanation of "(b)", refer to Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." *1: 5 when branching, 4 when not branching *2: 7 when condition is satisfied, 6 when not satisfied *3: Undefined count *4: Until condition is satisfied 52 To Top / Lineup / Index MB90242A Series Table 24 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) Byte code extension Word code extension Byte zero extension Word zero extension LH AH - - X - Z - - * - X - Z I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C RMW - - - - - - - - - - - - # cycles B 1 1 1 1 1 1 3 2 1 2 1 2 0 0 0 0 0 0 Table 25 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FILS/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI m: *1: *2: *3: *4: *5: *6: *7: *8: # cycles B 2 2 2 2 *2 *2 *1 *1 String Instructions [10 Instructions] Operation LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - T - - - - - - - - - - N - - * * * - - * * * Z - - * * * - - * * * V - - * * - - - * * - C RMW - - * * - - - * * - - - - - - - - - - - *3 Byte transfer @AH+ @AL+, counter = RW0 *3 Byte transfer @AH- @AL-, counter = RW0 *4 Byte retrieval @AH+ - AL, counter = RW0 *4 Byte retrieval @AH- - AL, counter = RW0 2 5m +3 *5 Byte filling @AH+ AL, counter = RW0 2 2 2 2 *2 *2 *1 *1 *6 Word transfer @AH+ @AL+, counter = RW0 - *6 Word transfer @AH- @AL-, counter = RW0 - *7 Word retrieval @AH+ - AL, counter = RW0 *7 Word retrieval @AH- - AL, counter = RW0 - - - 2 5m +3 *8 Word filling @AH+ AL, counter = RW0 RW0 value (counter value) 3 when RW0 is 0, 2 + 6 x (RW0) for count out, and 6n + 4 when match occurs 4 when RW0 is 0, 2 + 6 x (RW0) in any other case (b) x (RW0) (b) x n (b) x (RW0) (c) x (RW0) (c) x n (c) x (RW0) 53 To Top / Lineup / Index MB90242A Series Table 26 Mnemonic @A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @A, @RLi, #imm8 @A, eam, #imm8 addr16, @RLi, #imm8 addr16, eam, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 @RLi, @A, #imm8 eam, @A, #imm8 @RLi, addr16, #imm8 eam, addr16, #imm8 bnk : addr16, *5 bnk : addr16, #imm8 MOVMW bnk : addr16, *5 bnk : addr16, #imm8 MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM MOVM MOVM MOVM MOVMW MOVMW MOVMW MOVMW MOVM Multiple Data Transfer Instructions [18 Instructions] Operation Multiple data trasfer byte ((A)) ((RLi)) Multiple data trasfer byte ((A)) (eam) Multiple data trasfer byte (addr16) ((RLi)) Multiple data trasfer byte (addr16) (eam) Multiple data trasfer word ((A)) ((RLi)) Multiple data trasfer word ((A)) (eam) Multiple data trasfer word (addr16) ((RLi)) Multiple data trasfer word (addr16) (eam) Multiple data trasfer byte ((RLi)) ((A)) Multiple data trasfer byte (eam) ((A)) Multiple data transfer byte ((RLi)) (addr16) Multiple data transfer byte (eam) (addr16) Multiple data trasfer word ((RLi)) ((A)) Multiple data trasfer word (eam) ((A)) Multiple data transfer word ((RLi)) (addr16) Multiple data transfer word (eam) (addr16) Multiple data transfer byte (bnk:addr16) (bnk:addr16) Multiple data transfer word (bnk:addr16) (bnk:addr16) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - N - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - - - - - - - V - - - - - - - - - - - - - - - - - - C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # cycles B 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7 * *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *2 *1 *1 1 * *3 *3 *3 *4 *4 *4 *4 *3 *3 *3 *3 *4 *4 *4 *4 *3 *4 3 *1: 5 + imm8 x 5, 256 times when imm8 is zero. *2: 5 + imm8 x 5 + (a), 256 times when imm8 is zero. *3: Number of transfers x (b) x 2 *4: Number of transfers x (c) x 2 *5: The bank register specified by "bnk" is the same as for the MOVS instruction. 54 To Top / Lineup / Index MB90242A Series s ORDERING INFORMATION Part number MB90242A Package 80-pin Plastic LQFP (FPT-80P-M05) Remarks 55 To Top / Lineup / Index MB90242A Series s PACKAGE DIMENSIONS 80-pin Plastic LQFP (FPT-80P-M05) 14.000.20(.551.008)SQ 60 12.000.10(.472.004)SQ 1.50 -0.10 (Mounting height) +.008 .059 -.004 41 +0.20 61 40 9.50 (.374) REF INDEX 80 21 13.00 (.512) NOM LEAD No. 1 20 "A" 0.127 -0.02 +.002 .005 -.001 +0.05 Details of "A" part 0.500.08 (.0197.0031) 0.18 -0.03 +.003 .007 -.001 +0.08 0.100.10 (STAND OFF) (.004.004) 0.500.20(.020.008) 0.10(.004) 0 10 C 1995 FUJITSU LIMITED F80008S-2C-5 Dimensions in mm (inches) 56 To Top / Lineup / Index MB90242A Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9704 (c) FUJITSU LIMITED Printed in Japan 57 |
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